FIELD OF THE INVENTION
The present invention relates to a method for fabricating a capacitor for a semiconductor memory configuration.
In semiconductor memory configurations such as, by way of example, dynamic random access memories (DRAMs) or ferroelectric random access memories (FRAMs), the area occupied by a storage capacitor should be as small as possible, but the capacitance of the storage capacitor should not fall below a minimum capacitance. In order to achieve this goal, diverse endeavors have already been undertaken to provide capacitors which meet this requirement.
As examples of the various types of capacitors known heretofore, reference shall be made to the below listed references.
German Patent DE 195 46 999 C1, corresponding to U.S. Pat. No. 5,817,553, describes a so-called FIN stacked cell in which, by utilizing the selective etchability of p.sup.+ -doped polysilicon and p.sup.- -doped polysilicon, a lamellar structure made of p.sup.+ -conducting polysilicon is produced, to which a counterelectrode is applied after the application of an insulating layer. The essentially horizontal lamellae make a substantial contribution to increasing the capacitance of such a capacitor. However, if the space occupied by the capacitor on an integrated circuit becomes smaller and smaller, the contribution of the lamellae to the capacitance decreases in above average fashion.
Furthermore, U.S. Pat. No. 5,196,364 discloses a stacked capacitor in which an electrode is configured in the shape of a finger and, with the interposition of a capacitor layer, is covered with a counterelectrode. In this case, the fingers are spread outward, which admittedly increases the capacitance of such a capacitor but, at the same time, also increases the space requirement of the capacitor on an integrated circuit.
While the two known capacitors described above are provided on an integrated circuit, a trench capacitor disclosed in IEDM 85, pages 702 to 705, is embedded in a semiconductor chip. One electrode of such a trench capacitor is formed by polysilicon that fills the trench and is isolated from the semiconductor chip acting as the counterelectrode by an insulating layer made of silicon dioxide, for example.
U.S. Pat. No. 5,095,346 discloses a so-called advanced block cell for a stacked capacitor in which two polycrystalline silicon layers, which form storage electrodes, are capacitively connected to one another. The respective layers are in this case patterned by etching.
Finally, European Patent EP 0 448 374 B1 also discloses using polycrystalline silicon with a surface which has microroughness in order to increase the capacitance in a capacitor. This surface has a microroughness and silicon grain sizes of between 30 and 50 .ANG. that enables the "plate area" of the capacitor to be readily increased without requiring additional space on the chip area.
As has already been mentioned above, the FIN stacked capacitor is particularly advantageous with regard to the capacitances that can be obtained. If the available area on the semiconductor chip decreases further, however, then the contribution that the lamellae or ribs can afford overall to the capacitance of the capacitor is smaller and smaller, with the result that the gain in capacitance caused by the lamellae or ribs does not necessarily justify the additional outlay required to fabricate the ribs.